Abstract: Many-body fermionic systems can be simulated in a hardware-efficient manner using a fermionic quantum processor. Neutral atoms trapped in optical potentials can realize such processors, where non-local fermionic statistics are guaranteed at the hardware level. Implementing quantum error correction in this setup is however challenging, due to the atom-number superselection present in atomic systems, that is, the impossibility of creating coherent superpositions of different particle numbers. In this work, we overcome this constraint and present a blueprint for an error-corrected fermionic quantum processor that can be implemented using current experimental capabilities. To achieve this, we first consider an ancillary set of fermionic modes and design a fermionic reference, which we then use to construct superpositions of different numbers of referenced fermions. This allows us to build logical fermionic modes that can be error corrected using standard atomic operations. Here, we focus on phase errors, which we expect to be a dominant source of errors in neutral-atom quantum processors. We then construct logical fermionic gates, and show their implementation for the logical particle-number conserving processes relevant for quantum simulation. Finally, our protocol is illustrated with a minimal fermionic circuit, where it leads to a quadratic suppression of the logical error rate.
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